sigil-kernel's eleventh HAL batch adds 8 more seams — four Apple Silicon and four PowerPC. Apple side: UltraFusion die-to-die interconnect (M1 Ultra, 2 dies, 32GB per die, cross-die transactions, E+P cluster affinity), USB-C mux alt-mode arbiter (4 ports, USB3/DP-Alt/TB4/USB4 priority select, partner capability → best mode), secure boot chain of trust (5-stage BootROM→LLB→iBoot→Kernel→User, PCR-style measurement extension, boot policy SIP/SSV/kext/debug), ProRes media engine (2-engine enc+dec, 4-deep frame queue, proxy/LT/normal/HQ quality tiers, byte estimator). PowerPC side: Grackle MPC106 PCI host bridge (4 slots, ATI Rage128 + Apple-USB + SMC-Ethernet, 66MHz bus), Heathrow Mac I/O (64-IRQ controller, 12-line GPIO, feature-ctrl), MACE Am79C940 Ethernet (MACCC promisc/TX/RX/loopback, 64-bit multicast, loopback TX→RX), CUDA PMU (battery/AC/lid, RTC Mac epoch, scheduled wake, thermal shutdown 80°C). All QEMU PASS. (sigil-kernel 2acd370, 7a7ca6c, 7853e76, 4535635)
apple_nvlink.sg — M1 Ultra UltraFusion Die-to-Die Interconnect (2acd370)
apple_nvlink.sg models the UltraFusion die-to-die interconnect used in the M1 Ultra — Apple's solution for doubling M1 Max dies into a single logical package. The seam tracks 2 dies, each with 32 GB of DRAM, along with per-die active status, credit availability, and accumulated bandwidth.
- Cross-die transaction model: a transaction drains one credit on the source die, accumulates TX bandwidth on the source, accumulates RX bandwidth on the peer die, and increments the hop counter.
- E+P cluster affinity: efficiency threads prefer die 0; performance threads prefer die 1. Affinity is expressed as a preference, not a hard binding — the scheduler can override.
- Base address
0x468000. PASS:NVL init=1 up=1 xact=1
apple_usbc_mux.sg — 4-Port USB-C Alt-Mode Multiplexer (7a7ca6c)
apple_usbc_mux.sg models the USB-C alt-mode mux arbiter that decides which protocol a given USB-C port carries at any moment — USB3, DisplayPort Alt, Thunderbolt 4, or USB4.
- Modes: USB3 (5/10 Gbps), DP-Alt (4-lane DisplayPort), TB4 (40 Gbps Thunderbolt 4), USB4 (40 Gbps USB4).
- Priority arbiter: TB4 > USB4 > DP-Alt > USB3. The partner capability field on each port drives best-mode selection — the highest-priority mode both sides support wins.
- Per-port state: DP-lanes (2 or 4), speed, live-tracking flag. Detach clears all port state.
- Base address
0x46A000. PASS:UCMX init=1 dp=1 tb=1
apple_secboot_chain.sg — 5-Stage Chain of Trust (7853e76)
apple_secboot_chain.sg models the OS-level chain-of-trust policy that Apple's Secure Enclave and SecureBoot.efi enforce at runtime — PCR-style measurements, SIP/SSV state, and kext policy.
- Stages: BootROM (0) → LLB (1) → iBoot (2) → Kernel (3) → User (4).
- PCR-style measurement extension: each stage's measurement is hashed into the running chain value, so the final PCR reflects the entire boot path.
- In-order enforcement: stages must attest in strict order; out-of-order attestation sets the FAULT flag.
- Boot policy flags: SIP (System Integrity Protection), SSV (Sealed System Volume), kext-allowed, debug-enabled.
- Base address
0x46C000. PASS:SBC init=1 cot=1 flt=1
Relationship to apple_secboot: apple_secboot (the HARD STOP fix, 6dfc207) models the iBoot-level FNV hash chain for the boot stages themselves. apple_secboot_chain models the OS-level chain-of-trust policy that SecureBoot.efi / Apple's Secure Enclave enforces at runtime — PCR measurements, SIP/SSV state, kext policy. Together they cover the full secure boot surface from hardware fuses to runtime kernel trust.
apple_prores.sg — M1 Pro/Max/M2 ProRes Hardware Media Engine (4535635)
apple_prores.sg models Apple's dedicated ProRes hardware acceleration engine present in M1 Pro, M1 Max, and M2. ProRes encoding and decoding bypass the GPU entirely, running on a fixed-function media engine.
- 2 engines: encoder (
enc) and decoder (dec), each with a 4-deep frame queue. - Quality tiers: Proxy (45 Mbps), LT (102 Mbps), Normal (147 Mbps), HQ (220 Mbps).
- Per-frame byte estimator: returns estimated bytes for a given quality tier and frame dimensions — useful for pre-allocating output buffers without running a full encode.
- Session open/close lifecycle. Base address
0x46E000. PASS:PR init=1 enc=1 byt=1
ppc_grackle.sg — G3 Grackle MPC106 PCI Host Bridge (2acd370)
ppc_grackle.sg models the Motorola MPC106 "Grackle" PCI host bridge used in the Power Macintosh G3 (Beige). The Grackle sits at the top of the PCI bus and exposes four downstream device slots.
Per-device state tracks vendor/device ID, class, and BAR0. A present-count field tracks how many slots are populated. 66 MHz PCI bus. Base address 0x469000. PASS: GK init=1 pop=1 cls=1
ppc_heathrow.sg — G3 Heathrow Mac I/O Hub (7a7ca6c)
ppc_heathrow.sg models the Apple Heathrow Mac I/O ASIC, the peripheral hub that connects the G3's CPU to its I/O devices via a single chip — much as Apple's later southbridge designs would do for the G4.
- 64-IRQ controller: two 32-bit mask/status/level register groups. Per-IRQ inject and clear operations.
- Feature-ctrl: enable/disable ETH, USB, SCC, SCSI, audio, and video subsystems independently — used at boot to gate power to unused blocks.
- GPIO: 12 lines — power-btn, status LED, mute, modem-present, and others. Clock gate support.
- Base address
0x46B000. PASS:HW init=1 irq=1 gpio=1
ppc_mace.sg — G3 MACE Am79C940 Ethernet (7853e76)
ppc_mace.sg models the AMD Am79C940 MACE (Media Access Controller for Ethernet) used in the original Macintosh G3. This is a classic 10BASE-T/AUI integrated Ethernet controller.
- MACCC register: promiscuous mode, TX enable, RX enable, loopback mode — the four fundamental MAC control bits.
- PHYSEL: AUI or 10BASE-T media selection.
- 48-bit MAC address: stored as three 16-bit words. 64-bit multicast filter.
- TX + RX frame counters. Loopback: TX frame mirrors to RX buffer for self-test — the
ppc_maceseam verifies this path explicitly. - Base address
0x46D000. PASS:MACE init=1 lb=1 mac=1
ppc_pmu.sg — G3/G4 CUDA PMU Power Management Unit (4535635)
ppc_pmu.sg models the CUDA PMU (Power Management Unit) embedded in G3 and G4 Power Macintosh systems. CUDA handles battery/AC state, RTC, scheduled wake, keyboard backlight, and thermal shutdown — the full system power surface below the OS.
- Battery state: capacity %, voltage (mV), current (mA), health %.
- AC presence, lid open/close, power-button state.
- RTC: Mac epoch seconds — seconds since January 1, 1904 (the classic Mac time origin).
- Scheduled wake alarm: an epoch-seconds value that triggers a wake from S3/S5 at a specific time.
- S0/S3/S5 power states. Keyboard backlight duty cycle (0–255).
- Thermal shutdown at 80°C (configurable threshold).
- Base address
0x46F000. PASS:PMU init=1 slp=1 thm=1
HAL seam summary — batch 11
| Seam file | Commit | Platform | Address | PASS |
|---|---|---|---|---|
apple_nvlink.sg | 2acd370 | Apple Silicon (M1 Ultra) | 0x468000 | NVL init=1 up=1 xact=1 |
ppc_grackle.sg | 2acd370 | PowerPC G3 | 0x469000 | GK init=1 pop=1 cls=1 |
apple_usbc_mux.sg | 7a7ca6c | Apple Silicon | 0x46A000 | UCMX init=1 dp=1 tb=1 |
ppc_heathrow.sg | 7a7ca6c | PowerPC G3 | 0x46B000 | HW init=1 irq=1 gpio=1 |
apple_secboot_chain.sg | 7853e76 | Apple Silicon | 0x46C000 | SBC init=1 cot=1 flt=1 |
ppc_mace.sg | 7853e76 | PowerPC G3 | 0x46D000 | MACE init=1 lb=1 mac=1 |
apple_prores.sg | 4535635 | Apple Silicon (M1 Pro/Max/M2) | 0x46E000 | PR init=1 enc=1 byt=1 |
ppc_pmu.sg | 4535635 | PowerPC G3/G4 | 0x46F000 | PMU init=1 slp=1 thm=1 |