Five commits land 10 new HAL seams across two architectures: five M1 components completing the Apple Silicon power and security surface, and five G3/G4/G5 components rounding out the PowerPC legacy platform. All QEMU PASS. (sigil-kernel 86c7f17, 0c86726, e8555fb, e1ede63, 632f8ad)
Apple Silicon — Batch 5
Five new M1 seams covering the remaining power, security, and connectivity subsystems needed for kernel bring-up on real silicon.
apple_pmu.sg (86c7f17)
ARMv8 PMU — 8 event counters + cycle counter. Configure/inject event codes (INST / L1D-MISS / L2). Enable/reset. Base 0x43B000. PASS: PMU init=1 cfg=1 cnt=1 cyc=1
apple_cpufreq.sg (0c86726)
CPU P-state frequency scaling — E-cluster (600–2064 MHz, 5 P-states) + P-cluster (600–3204 MHz, 8 P-states). P-state lookup via in-DRAM freq tables. Base 0x43D000. PASS: PSTATE init=1 eff=1 perf=1
apple_panic.sg (e8555fb)
Crash log seam — 256 B slot, DEADFACE magic, 7-field record (type: DABORT / WDOG / ASSERT; PC; LR; ESR; FAR; task; epoch). Clear/valid probe. Base 0x43F000. PASS: PANIC init=1 rec=1 type=1
apple_keystore.sg (e1ede63)
SEP keystore — 8-slot AES256/ECDH384/HMAC256, gen/use-count/delete, biometric-protected flag, lock/unlock state. Base 0x442000. PASS: KS init=1 gen=1 use=1 lock=1
apple_nfc.sg (632f8ad)
NFC (PN553) + UWB (U1) combined seam — NFC power/poll/tag-inject, ISO14443A tag detect, NDEF len; UWB ranging 150 cm @ 45°, peer ID. Base 0x443000. PASS: NFCUWB init=1 nfc=1 uwb=1
PowerPC — Batch 5
Five G3/G4/G5 seams closing out the legacy platform surface: memory controller, SIMD detection, interrupt controller, L2 cache, and platform power management.
ppc_sdram.sg (86c7f17)
G3/G4 Uni-N SDRAM — PC133 CAS3 timing, 4-slot 512 MB, per-bank size, total_mb accumulate. Base 0x43C000. PASS: SDRAM init=1 bank=1 tot=1
ppc_altivec.sg (0c86726)
AltiVec/VMX — PVR-based detection (G4 7450 = present, 604 = absent), VRSAVE lazy context-switch, ctx-save counter. Base 0x43E000. PASS: AV init=1 no=1 ctx=1
ppc_mpic.sg (e8555fb)
G4/G5 MPIC (OpenPIC v2+) — 32 sources × IVPR/IDR, 2-CPU CTPR, route + priority set, EOI model. Base 0x440000. PASS: MPIC init=1 route=1 prio=1
ppc_l2cache.sg (e1ede63)
G3 750FX / G4 7450 L2 cache — enable/disable, cpu/2 or cpu/3 clock, hit/miss counters, hit-rate %, HW flush. Base 0x441000. PASS: L2C init=1 en=1 hr=1 fl=1
ppc_pmu.sg (632f8ad)
G3/G4 Cuda PMU — AC/charging/battery-85%, AC-remove simulation, sleep/wake cycle with fan-off/restore. Base 0x444000. PASS: GPMU init=1 batt=1 slp=1
HAL coverage complete
After 5 batches, both the M1 and G3/G4/G5 HAL layers cover every major subsystem needed for kernel bring-up. The batch results read clean:
| Seam | Platform | Commit | Result |
|---|---|---|---|
apple_pmu.sg | M1 | 86c7f17 | PMU init=1 cfg=1 cnt=1 cyc=1 |
ppc_sdram.sg | G3/G4 | 86c7f17 | SDRAM init=1 bank=1 tot=1 |
apple_cpufreq.sg | M1 | 0c86726 | PSTATE init=1 eff=1 perf=1 |
ppc_altivec.sg | G3/G4 | 0c86726 | AV init=1 no=1 ctx=1 |
apple_panic.sg | M1 | e8555fb | PANIC init=1 rec=1 type=1 |
ppc_mpic.sg | G4/G5 | e8555fb | MPIC init=1 route=1 prio=1 |
apple_keystore.sg | M1 | e1ede63 | KS init=1 gen=1 use=1 lock=1 |
ppc_l2cache.sg | G3/G4 | e1ede63 | L2C init=1 en=1 hr=1 fl=1 |
apple_nfc.sg | M1 | 632f8ad | NFCUWB init=1 nfc=1 uwb=1 |
ppc_pmu.sg | G3/G4 | 632f8ad | GPMU init=1 batt=1 slp=1 |
The pattern across all five batches: every seam is QEMU-modeled; real-silicon integration replaces the loopback stubs at the link seam — no code changes in the component files themselves. The HAL boundary is the contract; the stub and the silicon implementation are interchangeable behind it.