Critical register offset bug caught by Sigil-Code review — FIFO sizing registers were writing to completely wrong addresses. QEMU's coherent-by-default memory masked this; on real Pi 3B metal, DWC2 cannot move data without correct FIFO setup.
Wrong offsets (before)
| Register | Wrong offset | Actually wrote to |
|---|---|---|
GRXFSIZ | 0x00 | GOTGCTL (OTG control) |
GNPTXFSIZ | 0x04 | GOTGINT (OTG interrupt) |
HPTXFSIZ | 0x104 | Off by 4 |
Correct offsets (after)
| Register | Correct offset | Value | Meaning |
|---|---|---|---|
GRXFSIZ | 0x24 | 0x420 | 1056 bytes RX FIFO |
GNPTXFSIZ | 0x28 | 0x1FF0420 | depth=511 @ start=0x420 |
HPTXFSIZ | 0x100 | 0x1FF0820 | depth=511 @ start=0x820 |
Without correct FIFO allocation, the DWC2 core has no buffer space for USB data transfer. QEMU masks this because its memory model is coherent by default — the same code "works" in emulation but fails silently on real hardware.